Lu Peng

I received my Bachelor's and Master’s degrees in Computer Science & Engineering from Shanghai Jiaotong University, China. After that, I obtained a Ph.D. degree in Computer Engineering from the University of Florida in Spring 2005. My research area is computer systems and architecture focusing on many design issues on CPUs and GPUs, quantum processors, accelerators and applications for deep learning neural networks, and blockchain and its applications. My works were published in diverse conferences and journals including ISCA, HPCA, PPoPP, DAC, ICS, IPDPS, SRDS, and multiple IEEE/ACM journals. I received an ORAU Ralph E. Powe Junior Faculty Enhancement Award in 2007 and the Best Paper Award from IEEE International Green and Sustainable Computing Conference (IGSC) in 2019 and IEEE International Conference on Computer Design (ICCD) processor architecture track in 2001. I am a senior member of the IEEE and the ACM.

Selected Publications

W. Zhang, C. Zhao, L. Peng, Y. Lin, F. Zhang, and Y. Lu, "Boosting Performance and QoS for Concurrent GPU B+trees by Combining-based Synchronization," in Proceedings of the 28th ACM SIGPLAN Annual Symposium on Principles and Practice of Parallel Programming (PPoPP), Montreal, Canada, Feb. 2023.

T. Lu,  F. Qi, J. Ner, T. Feng, B. Cunningham, and L. Peng, "GeauxTrace: A Scalable Privacy-Protecting Contact Tracing App Design Using Blockchain," in Proceedings of the 9th IEEE/ACM International Conference on Big Data Computing, Applications and Technologies (BDCAT), Vancouver, WA, Dec. 2022.

F. Lin, X. Yuan, L. Peng, and N.-F. Tzeng, “Cascade Variational Auto-Encoder for Hierarchical Disentanglement,” In Proceedings of 31st ACM International Conference on Information and Knowledge Management (CIKM), October 2022.

T. LeCompte, F. Qi, and L. Peng, “Robust Cache-Aware Quantum Processor Layout,” In Proceedings of the 39th IEEE International Symposium on Reliable Distributed Systems (SRDS), Shanghai, China, Sep. 2020.

T. Lu and L. Peng, “BPU: A Blockchain Processing Unit for Accelerated Smart Contract Execution,” In Proceedings of the 57th ACM/IEEE Annual Design Automation Conference (DAC), San Francisco, CA, Jul. 2020.

S. Chen, F. Zhang, L. Liu, and L. Peng, “Efficient GPU NVRAM Persistence with Helper Warps,” In Proceedings of the 56th ACM/IEEE Annual Design Automation Conference (DAC), Las Vegas, NV, Jun. 2019.

Z. Yan, Y. Lin, L. Peng, W. Zhang, “Harmonia: A High Throughput B+tree for GPUs,” In Proceedings of the 24th ACM SIGPLAN Annual Symposium on Principles and Practice of Parallel Programming (PPoPP), Washington DC, Feb. 2019.

S. Chen, L. Peng, and S. Irving, “Accelerating GPU Hardware Transactional Memory with Snapshot Isolation,” In Proceedings of The ACM/IEEE 44th International Symposium on Computer Architecture (ISCA), Toronto, ON, Canada, Jun. 2017.

X. Xiang, W. Shi, S. Ghose, L. Peng, O. Mutlu, and N.-F. Tzeng, “Carpool: A Bufferless NoC with Adaptive Multicast and Hotspot Alleviation,” In Proceedings of the 31st ACM International Conference on Supercomputing (ICS), Chicago, IL, Jun. 2017.

S. Chen and L. Peng, “Efficient GPU Hardware Transactional Memory through Early Conflict Resolution,” In Proceedings of the 22nd IEEE International Symposium on High-Performance Computer Architecture (HPCA), Barcelona, Spain, Mar. 2016.

S.-M. Chen, Y. Hu, Y. Zhang, L. Peng, J. Ardonne, S. Irving, and A. Srivastava, “Increasing Off-Chip Bandwidth in Multi-Core Processors with Switchable Pins,” In Proceedings of The ACM/IEEE 41st International Symposium on Computer Architecture (ISCA), Minneapolis, MN, Jun. 2014.

Y. Zhang, L. Peng, X. Fu, and Y. Hu, “Lighting the Dark Silicon by Exploiting Heterogeneity on Future Processors,” In Proceedings of the 50th ACM/IEEE Annual Design Automation Conference (DAC), Austin, TX, Jun. 2013.

L. Duan, B. Li and L. Peng, “Versatile Prediction and Fast Estimation of Architectural Vulnerability Factor from Processor Performance Metrics,” In Proceedings of the 15th IEEE International Symposium on High-Performance Computer Architecture (HPCA), Raleigh, NC, Feb. 2009.

X. Shi, Z. Yang, J-K. Peir, L. Peng, Y-K. Chen, V. Lee, and B. Liang, “Coterminous Locality and Coterminous Group Data Prefetching on Chip-Multiprocessors”, In Proceedings of the 20th IEEE International Parallel & Distributed Processing Symposium (IPDPS), Rhodes Island, Greece. Apr. 2006.

L. Peng, J-K. Peir and K. Lai, “Signature Buffer: Bridging Performance Gap between Registers and Caches”, In Proceedings of the 10th IEEE International Symposium on High-Performance Computer Architecture (HPCA), Madrid, Spain, Feb. 2004.